The present disclosure relates to a clock data recovery circuit, a data reception apparatus, and a data transmission and reception system.
In the fields of information apparatus and digital apparatus in recent years, for transmitting a large volume of digital data at high speed and low cost, high-speed serial communication is widely used. A reception apparatus of the speed serial communication uses a “clock and data recovery” circuit (hereinafter, abbreviated as “CDR”) to reproduce clock and data synchronized with a reception data column subjected to predetermined encoding. In order to extract a data rate of the reception data column, a transmitter transmits a predetermined clock pattern before the data column to be transmitted and the CDR is synchronized with the clock pattern, to thereby lock a clock frequency of the CDR to a predetermined frequency.
FIG. 10 is a block diagram of a CDR 1001 in the related art.
A reception data signal DIN is input into each of a phase comparator 102, a frequency phase comparator 104, and a lock detector 106.
The frequency phase comparator 104 compares a frequency and a phase of a feedback clock signal FBCLK obtained by dividing a clock signal VCOCLK output from a voltage control oscillator 105 by a divider 108 at a predetermined division ratio, with a frequency and a phase of a clock pattern of the reception data signal DIN, and outputs a control signal corresponding to a comparison result thereof.
The phase comparator 102 compares a phase of the clock signal VCOCLK output from the voltage control oscillator 105 with a phase of a data column or the clock pattern of the reception data signal DIN, and outputs a control signal corresponding to a comparison result thereof. Further, the phase comparator 102 outputs a reproduction data signal RDATA synchronized with the clock signal VCOCLK.
The lock detector 106 compares the frequency and phase of the clock signal VCOCLK with the frequency and phase of the clock pattern of the reception data signal DIN, and determines whether or not the frequency and phase of the clock signal VCOCLK approach the frequency and phase of the clock pattern of the reception data signal DIN such that a loop including the phase comparator 102, which will be described later, is in a frequency range, in other words, whether or not the lock is achieved. If the lock detector 106 detects the lock (frequency pull-in operation is completed), the lock detector 106 provides a logic signal (determination signal SEL) indicating the “lock detection” to each of multiplexers 109a and 109b 
Each of the multiplexers 109a and 109b receives the determination signal of the lock detector 106, and provides an output signal of the frequency phase comparator 104 or an output signal of the phase comparator 102 to a first charge pump circuit 110. The first charge pump circuit 110 receives the pulsed output signal output from the frequency phase comparator 104 or the phase comparator 102, and outputs a pulsed current signal. The current signal is integrated and converted into a voltage signal by the loop filter 111 being a low-pass filter such that an unnecessary high-frequency component is removed. After that, the voltage signal is input into the voltage control oscillator 105. The voltage control oscillator 105 oscillates a signal having a frequency corresponding to the input voltage signal. The clock signal VCOCLK output by the voltage control oscillator 105 is input into the phase comparator 102 and into the frequency phase comparator 104 and the lock detector 106 via the divider 108.
The reproduction data signal RDATA output from the phase comparator 102 and the clock signal VCOCLK output by the voltage control oscillator 105 are supplied to a deserializer 910 (see FIG. 9) at the subsequent stage.
Note that a document that discloses a technique considered to be relevant to the present disclosure is Japanese Patent Application Laid-open No. HEI 8-237240 (hereinafter, referred to as Patent Document 1). Patent Document 1 discloses technical contents of a method for generating a clock pulse, a clock pulse generator, and a clock regenerating circuit capable of automatically and easily adjusting the frequency range of a voltage controlled oscillator and avoiding erroneous synchronization irrespective of its time of generation.